1. Field of the Invention
This invention relates to integrated circuit devices, and more specifically to an insulation means useful in the construction of integrated circuits containing capacitors and dual layer electrical interconnects.
2. Description of the Prior Art
Prior art devices utilizing dual aluminum metalization layers are described in U.S. Pat. Nos. 3,931,674 and 3,586,922. A cross sectional view of a typical prior art integrated circuit device is also shown in FIG. 1. On semiconductor substrate 11 is formed insulation region 99 (preferably silicon dioxide) and polycrystalline silicon region 12 preferably selectively doped to a desired conductivity. Isolation oxide regions 13 are then formed surrounding polycrystalline silicon (polysilicon) region 12. A thin oxide layer 14 is formed (typically either deposited or thermally grown) directly over polysilicon layer 12, typically by thermal oxidation. Aluminum layer 15 is then formed over oxide layer 14. In this fashion, a prior art capacitor is formed having a first plate comprising polysilicon region 12, a second plate comprising aluminum region 15, and a dielectric formed therebetween comprising silicon dioxide (commonly referred to as "oxide") region 14. In order to form an effective capacitor utilizing this prior art method, oxide region 14 must be quite thin, typically on the order of 600 angstroms.
The same technique may be utilized to form an integrated circuit with dual layer electrical interconnects. In this case, however, oxide layer 14 is grown to be much thicker than the thickness utilized when forming capacitors. For example, oxide layer 14 is typically formed to a thickness of approximately 2000-6000 angstroms when polysilicon region 12 and aluminum region 15 are to be used as dual layer interconnects, rather than as a capacitor.
The primary disadvantage in forming dual layer interconnects or capacitors for use in integrated circuits utilizing this prior art technique is the presence of defects or pin holes in oxide layer 14. Such a defect or pin hole will result in a reduced oxide thickness. If a pin hole is present in oxide layer 14, the dielectric strength of oxide layer 14 will be greatly reduced, thus allowing electrical breakdown of layer 14 and the resultant formation of shorts between polysilicon region 12 and aluminum region 15. In the case of a severe pin hole, a portion of polysilicon region 12 will not be covered by oxide 14 and aluminum region 15 will be formed in such a manner that aluminum will be placed in the pin hole and in direct contact with polysilicon region 12, thus forming a direct short circuit during fabrication. The presence of pin holes in oxide region 14 is a widespread problem in the manufacture of such prior art devices. The formation of low defect thin oxide regions is difficult, due to the presence of contaminants on the surface of polysilicon region 12. The formation of pin holes in oxide region 14 is further aggravated by chemical attacks upon oxide region 14 by chemicals used in subsequent processing, including the patterning of aluminum region 15. Typical etchants (eg. hydrofloric acid) used to pattern aluminum also attack the silicon oxide used as the dielectric in prior art capacitors.
The use of polycrystalline silicon to serve as a mask during doping of underlying regions has been taught by Amelio and Salsbury in U.S. Pat. No. 3,836,409. However, no mention is made of the use of portions of polycrystalline silicon to protect an underlying insulation layer from inadvertent chemical attack during subsequent processing.